1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices responsive to an external clock signal for operation, and more particularly to a structure for realizing high speed performance testing.
2. Description of the Background Art
A synchronous semiconductor memory device developed for the purpose of high speed access has the operation (command) required for data reading and writing carried out in synchronization with an externally applied clock (external clock signal) of a stable cycle.
A conventional synchronous semiconductor memory device will be described hereinafter with reference to FIG. 31.
Referring to FIG. 31, a conventional synchronous semiconductor memory device 9000 includes a control signal buffer 1, an internal clock generation circuit 2, an address buffer 3, a mode set specify circuit 4, a precharge signal generation circuit 12, an act signal generation circuit 13, and a plurality of banks (Banks B0, B1, B2 and B3 in FIG. 31).
Each of banks B0, B1, B2 and B3 includes a row related control circuit 6, a word driver 7, a memory cell array 9, a sense amplifier, and an IO gate. The sense amplifier and the IO gate are indicated as one block 8 in FIG. 31. Each bank can individually carry out activation of a word line, data reading, data writing, and inactivation of a word line.
Memory cell array 9 includes a plurality of memory cells M arranged in a matrix. Each memory cell M is connected at a crossing of a word line WL provided corresponding to a row direction and a bit line pair BL and /BL provided corresponding to a column direction. Internal clock generation circuit 2 receives an external clock signal CLK to output an internal clock signal CLK0 to control the internal operation.
Control signal buffer 1 includes a first input stage 16 and a buffer 17. First input stage 16 receives an external control signal (external row address strobe signal /RAS, external column address strobe signal /CAS, external write enable signal /WE, external chip select signal /CS, and the like). Buffer 17 receives an output of input stage 16 to output an internal control signal (RAS, CAS, WE, CS, and the like) in synchronization with internal clock signal CLK0.
Address buffer 3 receives an externally applied address signal A to output an internal address signal. Address signal A is applied having a row address signal X and a column address signal Y multiplexed in a time-divisional manner. Address buffer 3 further includes a bank address decoder not shown for decoding address signal A to output a bank decode signal BK (or an inverted version ZBK) specifying a corresponding bank.
Act signal generation circuit 13 responds to an externally applied act command to output an act initiation signal ZACT (in FIG. 31, ZACT(0), ZACT(1), ZACT(2), ZACT(3)) for controlling a row related control circuit 6 of a specified bank.
Precharge signal generation circuit 12 responds to an externally applied precharge command to output a precharge initiation signal ZPRE (in FIG. 31, ZPRE(0), ZPRE(1), ZPRE(2), ZPRE(3)) for a controlling row related control circuit 6 of a specified bank.
Upon receiving a corresponding act initiation signal ZACT, each row related control circuit 6 outputs a precharge signal for precharging a corresponding bit line in an inactive state, a word driver activation signal for activating word driver 7 in an active state, and a sense amplifier activation signal for activating the sense amplifier at an active state.
As a result, the pair of bit lines BL and /BL forming memory cell array 9 is released from the precharged state, and word line WL is driven to an H level (logical high). Then, the data stored in memory cell M is amplified by the sense amplifier.
Each row related control circuit 6 also responds to a corresponding precharge initiation signal ZPRE to output a word driver activation signal in an inactive state, a sense amplifier activation signal in an inactive state, and a bit line precharge signal in an activation state. As a result, the potential of word line WL in memory cell array 9 is pulled down to an L level (logical L), and bit lines BL and /BL are precharged to the level of a precharge potential Vb1.
When an externally applied read command is input, the data latched at the sense amplifier is transmitted to the IO gate, and then amplified to be output through a data input/output terminal.
When an external write command is input, the data applied through the data input/output terminal is written into a relevant memory cell M via the IO gate and the sense amplifier.
Mode set specify circuit 4 functions to detect whether a particular mode is set in response to an external signal. Mode set specify circuit 4 responds to a signal from control signal buffer 1 and address buffer 3 (for example, a mode register set command + address signal ADD7 of an H level) to output a test mode signal. There is also a method of setting a test mode signal by direct control of an external test mode PAD.
An operation of conventional synchronous semiconductor memory device 9000 will be described with reference to the timing charts of FIGS. 32A-32F.
FIGS. 32A, B, C, D, E and F show an external clock signal CLK, an external control signal ICS, an external control signal /RAS, an external control signal /CAS, an external control signal /WE, and an address signal A, respectively. Here, chip select signal /CS is a control signal for selecting a chip to be operated out of a plurality of chips. In the following command input operation, a chip select signal ICS attains an active state of an L level.
The operation of activating a word line by an active command will be described first. In this case, an act command ACT is input (external control signals /CS and /RAS are set at an L level, and external control signals /CAS and /WE are set at an H level).
At time t1 when external clock signal CLK rises, these external control signals and row address signal X are received. Then, a word line of a corresponding bank is activated according to act initiation signal ZACT output from act signal generation circuit 13, whereby the data in memory cell M is read out to the sense amplifier.
An operation of a readout command will be described hereinafter. In this case, a read command READ is input (external control signal ICS and /CAS are set at an L level, and external control signals /RAS and /WE are set at an H level.
At the next rise of external clock signal CLK (time t2), these external control signals and column address signal Y are input. As a result, the data readout to the sense amplifier is applied to an output buffer not shown via an I/O line to be provided outside.
The operation of rendering a word line inactive by a precharge command will be described hereinafter. In this case, a precharge command PRE is input (external control signals ICS and /RAS, and /WE are set at an L level, and external control signal ICAS is set at an H level).
At the rise of external clock signal CLK at time t3, these external signals and bank address signal BK are input. Then, a corresponding word line is rendered inactive according to precharge initiation signal ZPRE output from precharge signal generation circuit 12.
At the next rise of external clock signal CLK (time t4), input of act command ACT renders a corresponding word line active, whereby the data in memory cell M is readout to the sense amplifier.
The duration between the sense amplifier activation time t1 and read out time R2 becomes a parameter for identifying the performance of a memory cell (this period is referred to as "tRCD period" hereinafter). For example, in a memory cell of an extremely small capacity, the sensing time by the sense amplifier is longer than that of a memory cell of a normal capacity. A fault of a memory cell can be discovered at an early stage by altering the tRCD period.
The duration between word line inactivation time t3 and reactivation time t4 (this duration is referred to as "tRP period" hereinafter) becomes an important timing for identifying the effect of the equalize timing of a bit line. For example, when activation of a word line is initiated before a bit line is sufficiently equalized after the fall of a word line, there is a possibility that the stored information to be read out will be destroyed by activation of a new word line due to the previous data remaining in the bit line. In general, 20 ns must be ensured for the tRCD period and tRP period.
When testing the performance of a synchronous semiconductor memory device of the above-described structure, an external clock signal and a command are provided from a tester. When the threshold performance is to be tested under the most critical conditions, a command is input at the edge of a continuous external clock signal (clock signal supplied by tester) as shown in FIG. 32. Accordingly, the shortest tRCD and tRP periods are realized, so that the threshold performance can be tested by identifying the operation characteristics in this state.
The input timing of a command to conventional synchronous semiconductor memory device 9000 depends upon the frequency of the clock signal that is constantly provided from the tester. This means that the tRCD and tRP periods depend (upper limit approximately 200 ns) on the threshold performance (approximately 200 ns) of the tester when the tester can provide only a clock signal of a low speed. There was a problem that it is difficult to identify the threshold performance of a device that operates at high speed.